HDMP-1012 Datasheet, PDF (32/42 Pages) Agilent(Hewlett-Packard) – 4Low Cost Gigabit Rate Transmit/Receive Chip Set

SEND FF0
0
DISABLE DATA TRANSMISSION
DISABLE DATA RECEPTION
FREQUENCY DETECTOR ON
FF1
ERROR
FF0
RESET
SEND FF1
FF0
ERROR
RESET
1
DISABLE DATA TRANSMISSION
ENABLE DATA RECEPTION
FREQUENCY DETECTOR OFF
DATA
FF1
SEND FF0
ENABLE DATA TRANSMISSION
2
ENABLE DATA RECEPTION
FREQUENCY DETECTOR OFF
DATA
ERROR
RESET
FF0
DATA
FF1
Figure 15. HDMP-1014 (Rx) State Machine State Diagram.
When the local port is in State 0,
it is in the reset state, where both
local Tx and Rx parallel interfaces
are disabled. The local Tx
transmits FF0 continuously, and
the local Rx PLL is in the
frequency detection mode. When
the local Rx is phase-locked to the
remote Tx, it transitions to State
1. The local Tx transmits FF1 to
acknowledge the phase-locked
condition (its parallel input is still
disabled). The local Rx PLL is in
the phase detection mode and its
parallel output is enabled. When
in State 2, the two-way
synchronization between the local
port and the remote port is
established. Both local Tx and Rx
parallel interfaces are enabled,
and the local Rx PLL is in the
phase detection mode. Parallel
data can be sent by the local Tx,
and at the same time, received by
the local Rx.
The Rx chip has the state machine
logic built in. The SMC has two
status outputs, STAT0 and STAT1,
that control the various features
of the two chips depending on the
current state. The TX inputs that
need to be controlled are FF and
ED. The RX inputs that need to be
controlled are FDIS and ACTIVE.
To control the chips as shown in
the state diagram of Figure 15,
the following interchip
connections must be made
(Figure 16):
• Tx FF is driven by STAT1
• Tx ED is driven by STAT0
• Rx FDIS is driven by STAT1
• Rx ACTIVE is driven by STAT1
• TX RST and RX SMCRST0 are
driven by a power-on, or user,
reset circuit.
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