HDMP-1012 Datasheet, PDF (17/42 Pages) Agilent(Hewlett-Packard) – 4Low Cost Gigabit Rate Transmit/Receive Chip Set

Tx I/O Definition (cont’d.)
Name
INV
LOCKED
LOOPEN
LOUT
LOUT*
M20SEL
MDFSEL
RFD
RST*
STRBIN
STRBIN*
Pin Type
Signal
25 O-ECL Invert Signal: A high value of INV implies that the current frame is
being sent inverted to maintain long-term DC balance. With a buffer,
or pulled down with a 1K resistor to V_EE and ac coupled, this signal
is useful as an aid to analyzing the serial output stream with an
oscilloscope.
75 O-ECL Loop In-lock Indication: This signal indicates the lock status of the
Tx PLL. A high value indicates lock. This signal is normally connected
to the SMTRST1 reset input of the Rx state machine to force the link
into the start-up state until the Tx PLL has locked. This signal may
give multiple false-lock indications during the acquisition process, so
should be debounced if it is used for any other purpose than to drive
the Rx chip.
16 I-ECL Loop Back Control: Input which controls whether the DOUT,
DOUT*, or the LOUT, LOUT* outputs are currently enabled. If active,
LOUT, LOUT* are enabled. The unused output is powered down to
reduce dissipation.
14 O-BLL Loop Back Serial Data Output: Output used when LOOPEN is
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active. Typically this output will be used to drive the LIN, LIN* inputs
of the Rx chip.
73 I-ECL 16 or 20 Bit Word Select: When this signal is high, the link operates
in 20 Bit data transmission mode. Otherwise, the link operates in
16 Bit mode.
74 I-ECL Select Double Frame Mode: When this signal is high, the PLL
expects a 1/2 speed parallel clock at STRBIN. The chip then internally
multiplies this clock and produces a full-rate parallel clock at
STRBOUT. Note that the phase relationship of STRBIN to STRBOUT
and the sampling point change with asserting MDFSEL, as shown in
the Tx timing diagram. This feature is provided so that either a 40 bit
or 32 bit word can be easily transmitted as two 20, or two 16 bit
words. When MDFSEL is low, the PLL expects a full-rate parallel
clock at STRBIN.
65 O-ECL Ready for Data: Output to tell the user the Link is ready to
transmit data. This pin is a retimed version of the ED input, which is
driven by the Rx chip state machine controller.
34 I-ECL Chip Reset: This active-low pin initializes the internal chip registers.
It should be asserted during power up for a minimum of 5 parallel-
rate clock cycles to ensure a complete reset.
8 I-H50 Data Clock Input: When EHCLKSEL is low, this input is phase
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locked and multiplied to generate the high speed serial clock. The chip
expects a clock frequency which is equal to the input frame rate if
MDFSEL (double frame mode) is low, and 1/2 the frame rate if
MDFSEL is high. When EHCLKSEL is high, the PLL is bypassed,
and STRBIN directly becomes the high speed serial clock. Refer to
the Tx Timing diagram for the phase relationship between STRBIN,
data and STRBOUT.
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