HDMP-1012 Datasheet, PDF (19/42 Pages) Agilent(Hewlett-Packard) – 4Low Cost Gigabit Rate Transmit/Receive Chip Set

Rx I/O Definition
Name
ACTIVE
BCLK
BCLK*
CAP0A
CAP0B
CAP1A
CAP1B
CAV*
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
DAV*
DIN
DIN*
DIV0
DIV1
Pin Type
Signal
25 I-ECL Chip Enable: This input is normally driven by the Rx state machine
output. The ACTIVE signal is internally retimed by STRBOUT and
presented to the user as the LINKRDY signal. This is how the Rx
state machine signals the user that the start-up sequence is complete.
9 O-BLL VCO Monitor Output: These pins provide access to the internal
8
VCO clock.
2
C Loop Filter Capacitor: CAP0A should be shorted to CAP0B. CAP1A
1
should be shorted to CAP1B. A loop filter capacitor of 0.1 µf must be
3
connected across the CAP0 and CAP1 inputs to increase the loop time
4
constant.
38 O-ECL Control Frame Available Output: This active-low output indicates
that the Rx chip data outputs are receiving Control Frames. False
CAV indications may be generated during link startup.
71 O-ECL Data Outputs: 20 Bit data is received and decoded when M20SEL is
70
active; otherwise 16 bit data is decoded and the D16-D19 bits
69
are undefined.
68
67
66
65
60
59
58
57
56
55
54
51
50
49
48
47
46
37 O-ECL Data Available Output: This active-low output indicates that the
Rx chip data outputs, D0..D19, have received data frames. Data
should be latched on the rising edge of STRBOUT. Note that during
link startup, false data indications may be given. The DAV* and
LINKRDY outputs can be used together to avoid confusion during
link startup.
15 I-H50 Normal Serial Data Input: This is the input used when LOOPEN
14
is not active. When LOOPEN is high, the loop back data inputs LIN,
LIN* are used instead. An optional cable equalizer may be enabled for
the DIN, DIN* inputs by asserting EQEN.
6 I-ECL VCO Divider Select: These two pins program the VCO divider chain
7
to operate at full speed, half speed, quarter speed or one-eighth speed.
591