HDMP-1012 Datasheet, PDF (10/42 Pages) Agilent(Hewlett-Packard) – 4Low Cost Gigabit Rate Transmit/Receive Chip Set

HDMP-1012 (Tx) Timing
Figure 6 shows the Tx timing
diagram. Under normal
operations, the Tx PLL locks an
internally generated clock to the
incoming STRBIN. The incoming
data, D0-D19, ED, FF, DAV*,
CAV*, and FLAG, are latched by
this internal clock. For
MDFSEL=0, the input rate of
STRBIN is expected to be the
same as the parallel data rate. For
MDFSEL=1, STRBIN should be 1/
2 of the incoming parallel data
rate. The data must be valid
before it’s sampled for the set-up
time (t_s), and remain valid after
it’s sampled for the hold time (t_h).
The set-up and hold times are
referenced to STRBIN. This
reference is the positive edge of
STRBIN for MDFSEL=0, and is 1/
2 the frame period from the
positive or negative edge of
STRBIN for MDFSEL=1.
STRBOUT appears after this
reference with a delay of T_strb.
The rate of STRBOUT is always
the same as the word rate of the
incoming data, independent of
MDFSEL.
The start of a frame, D0, in the
high speed serial output occurs
after a delay of td after the rising
edge of the STRBIN. The typical
value of td may be calculated by
using the following formula:
td = ( 2 * serial bit duration -
0.5 ns) ns
HDMP-1012 (Tx) Timing Characteristics
Tc = 0°C to +85°C, V_EE = -4.5 V to -5.5 V
Symbol
Parameter
t_s
Setup Time, for Rising Edge of STRBIN Relative to
D0-D19, ED, FF, DAV*, CAV* and FLAG
t_h
∆T_strb
Hold Time, for Rising Edge of STRBIN Relative to
D0-D19, ED, FF, DAV*, CAV* and FLAG
STRBOUT - STRBIN Delay
Units Min. Typ. Max.
nsec
6
nsec
0
nsec
1.5 3
STRBIN
MDFSEL = 0
STRBIN
MDFSEL = 1
1/2 FRAME PERIOD
D00 - D19
ED, FF
DAV*, CAV*
FLAG
t_s
STRBOUT
DOUT
HCLK
t_strb
t_d
Figure 6. HDMP-1012 (Tx) Timing Diagram.
582
t_h
D-FIELD
C-FIELD