HDMP-1012 Datasheet, PDF (2/42 Pages) Agilent(Hewlett-Packard) – 4Low Cost Gigabit Rate Transmit/Receive Chip Set

and bit synchronization are
maintained. When data is not
available to send, the link
maintains synchronization by
transmitting fill frames. Two
(training) fill frames are reserved
for handshaking during link
startup.
User control space is also sup-
ported. If Control Available is
asserted at the Tx chip, the least
significant 14 or 18 bits of the
data are sent and the Rx Control
Available line will indicate the
data as a Control Word.
It is the intention of this data
sheet to provide the design
engineer all of the information
regarding the HDMP-1012/1014
chipset necessary to design this
product into their application. To
assist you in using this data sheet,
the following Table of Contents is
provided.
574
Table of Contents
Topic
Page
Typical Applications ....................................................................... 575
Setting the Operating Rate ..............................................................576
Transmitter Block Diagram .............................................................578
Receiver Block Diagram ................................................................. 580
Transmitter Timing Characteristics ................................................ 582
Receiver Timing Characteristics ..................................................... 583
DC Electrical Specifications ........................................................... 584
AC Electrical Specifications ............................................................ 584
Typical Lock-Up Times ................................................................... 584
Absolute Maximum Ratings ............................................................ 585
Thermal Characteristics ................................................................. 585
I/O Type Definitions ....................................................................... 585
Pin-Out Diagrams .......................................................................... 586
Transmitter Pin Definitions ............................................................ 587
Receiver Pin Definitions ................................................................. 591
Mechanical Dimensions and
Surface Mount Assembly Instructions ......................................... 595
Appendix I: Additional Internal
Architecture Information ........................................................596
Line Code Description .................................................................... 596
Data Frame Codes ......................................................................... 596
Control Frame Codes ..................................................................... 597
Fill Frame Codes ............................................................................ 598
Tx Operation Principles ................................................................. 599
Tx Encoding .................................................................................. 599
Tx Phase Locked Loop ....................................................................600
Rx Operation Principles ................................................................. 601
Rx Encoding ................................................................................... 601
HDMP-1014 (Rx) Phase Locked Loop ............................................ 601
HDMP-1014 (Rx) Decoding ............................................................602
HDMP-1014 (Rx) Link Control State
Machine Operation Principle ....................................................... 603
The State Machine Handshake Protocol ..........................................603
Appendix II: Link Configuration Examples ............................. 605
Duplex/Simplex Configurations ...................................................... 605
Full Duplex .....................................................................................605
Simplex Method I: Simplex with Low Speed Return Path ............... 606
Simplex Method II: Simplex with Periodic Sync Pulse ....................607
Simplex Method III: Simplex with
External Reference Oscillator ......................................................607
Data Interface for Single/Double Frame Mode ................................ 608
Single Frame Mode (MDFSEL=0) .................................................. 608
Double Frame Mode (MDFSEL=1) ................................................ 609
Supply Bypassing and Integrator Capacitor .................................... 610
Integrating Capacitor ......................................................................610
Power Supply Bypassing and Grounding ........................................ 610
Electrical Connections .................................................................... 611
I-ECL and O-ECL ............................................................................ 611
High Speed Interface: I-H50 & O-BLL ............................................612
TTL and Positive 5 V Operation ...................................................... 613
Mode Options ................................................................................. 614