HDMP-1012 Datasheet, PDF (34/42 Pages) Agilent(Hewlett-Packard) – 4Low Cost Gigabit Rate Transmit/Receive Chip Set

receive FF1, causing STAT0 to go
high, which asserts the enable
data (ED) pin on the Tx. The ED
signal is retimed to signify to the
host that the Tx is ready to send
data (RFD). Other configurations
for duplex mode are also possible
with external user-defined state
machines. Simplex operation
using G-LINK is also possible. The
following sections discuss three
different types of simplex
configurations.
Simplex Method I. Simplex
with Low-Speed Return Path
Low-speed lines are used in the
simplex method of Figure 17a.
The remote Rx controls the states
of both the Rx and the local Tx
using these low speed lines. This
is ideal for cases where these non-
critical lines are available. Again,
a power on reset is available to
the user. This connection between
the Tx and Rx is identical to one
side of the duplex configuration.
When the Tx is locked, the Rx is
enabled via the LOCKED line. The
Rx’s STAT0 and STAT1 outputs
are low, causing the local Tx to
send FF0. When the Rx is frame
locked, STAT1 is raised, which
disables its frequency detector,
sets itself to active mode, and tells
Tx to send FF1. Upon receiving
FF1 from the Tx, the Rx’s STAT0
line is raised, which enables the
Tx (ED) for data transmission. If
desired, the Rx reset pin
(SMCRST1) can be tied high, and
Tx DATA
INTERFACE
POWER-ON
RESET
Tx DATA
INTERFACE
POWER-ON RESET
PERIODIC
SYNC PULSES
Tx DATA
INTERFACE
POWER-ON
RESET
Tx
DOUT
LOUT
OPTIONS
DIN
LIN
OPTIONS
Rx
LOW SPEED LINES
A) SIMPLEX METHOD I WITH LOW-SPEED RETURN PATH
Tx
DOUT
LOUT
Rx
DIN
LIN
OPTIONS
OPTIONS
B) SIMPLEX METHOD II WITH PERIODIC SYNC PULSE
Tx
DOUT
Rx
LIN
LOUT
DIN
OSC
OPTIONS _{FREQ =} OPTIONS
FRAME RATE
C) SIMPLEX METHOD III WITH EXTERNAL REFERENCE OSCILLATOR
Rx DATA
INTERFACE
POWER-ON
RESET
Rx DATA
INTERFACE
POWER-ON
RESET
Rx DATA
INTERFACE
POWER-ON
RESET
Figure 17: Simplex Configurations.
606