HD66724 Datasheet, PDF (64/117 Pages) Hitachi Semiconductor – (Graphics LCD Controller/Driver with Key Scan Function)

HD66724/HD66725
Parallel Data Transfer
8-Bit Interface
Setting the IM2/1/0 (interface mode) to the GND/V_CC/GND level allows 68-system 8-bit parallel data
transfer. A direct interface using the 8-bit E-clock-synchronized bus or an interface via the I/O bus can be
established. Setting the IM2/1/0 to the V_CC/V_CC/GND level allows 80-system 8-bit parallel data transfer.
When the number of buses or mounting area is limited, use a 4-bit bus interface or serial data transfer.
Using a parallel bus interface disables the key scan function. To prevent this, use a clock-synchronized
serial interface.
*Interface via I/O port
C0
C1
H8/325
C2
8
A0–A7
E
RS
R/W
HD66724
HD66725
DB0–DB7
Figure 32 Interface to 8-Bit Microcomputer
4-Bit Interface
Setting the IM2/1/0 (interface mode) to the GND/V_CC/V_CC level allows 68-system 4-bit parallel data
transfer using pins DB7/KIN7-DB4/KIN4. Setting the IM2/1/0 to the V_CC/V_CC/V_CC level allows 80-system
4-bit parallel data transfer. 8-bit instructions and RAM data are divided into four upper/lower bits and
transfer starts from the upper four bits.
Using a parallel bus interface disables the key scan function. To prevent this, use a clock-synchronized
serial interface.
Note:
Transfer synchronization function for a 4-bit bus interface
The HD66724/HD66725 support transfer synchronization function which resets the upper/lower
counter to count upper/lower four-bit data transfer in the 4-bit bus interface. Noise causing transfer
mismatch between the four upper and lower bits can be corrected by a reset triggered by
consecutively writing a 0000 instruction four times. The next transfer starts from the upper four
bits. Executing synchronization function periodically can recover any runaway in the display
system.
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