HD66724 Datasheet, PDF (48/117 Pages) Hitachi Semiconductor – (Graphics LCD Controller/Driver with Key Scan Function)

HD66724/HD66725
Port Control
PT2-0: Controls the output level of a port output pin (PORT2-PORT0). When PT0 = 0, it specifies the
POT0 output to GND and when PT0 = 1, to VCC. Similarly, PT1 and PT2 bits control PORT1 and PORT2
output levels respectively.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 1 1 1 0 PT2 PT1 PT0
Figure 20 Port Control Instruction
RAM Address Set
RM1-0: Selects DDRAM, CGRAM, and SEGRAM. The selected RAM is accessed with this setting.
AD9-0: Initially sets RAM addresses to the address counter (AC). Once RAM data is accessed, the AC is
automatically updated according to the I/D bit. This allows consecutive accesses without resetting
addresses. RAM address setting is not allowed in the sleep mode or standby mode.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 0 RM1 RM0 AD9 AD8 AD7 AD6
0 0 1 1 ^{AD5 AD4 AD3 AD2 AD1 AD0}
Figure 21 RAM Address Set Instruction
Table 27 RM Bits and RAM Selection
RM1
0
0
1
1
RM0
0
1
0
1
RAM Selection
DDRAM
Setting inhibited
CGRAM
SEGRAM
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