HD66724 Datasheet, PDF (21/117 Pages) Hitachi Semiconductor – (Graphics LCD Controller/Driver with Key Scan Function)

HD66724/HD66725
Bits in SEGRAM corresponding to segments to be displayed are directly set by the MPU, regardless of the
contents of DDRAM and CGRAM.
Timing Generator
The timing generator generates timing signals for the operation of internal circuits such as DDRAM,
CGROM, CGRAM, and SEGRAM. The RAM read timing for display and internal operation timing by
MPU access are generated separately to avoid interference with one another. This prevents flickering in
areas other than the display area when writing the data to the DDRAM, for example.
Cursor/Blink Control Circuit
The cursor/blink (or black-white reversed) control is used to create a cursor or a flashing area on the
display in a position corresponding to the location stored in the address counter (AC).
1 2 3 4 5 6 7 8 9 10 11 12
00 01 02 03 04 05 06 07 08 09 0A 0B
Display position
DDRAM address
Cursor position
Note: The cursor/blink or black-white reversed control is
also active when the address counter indicates the
CGRAM or SEGRAM. However, it has no effect on the
display.
Figure 1 Cursor Position and DDRAM Address (When AC = 08H)
Oscillation Circuit (OSC)
The HD66724/HD66725 can provide R-C oscillation simply through the addition of an external oscillation-
resistor between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage,
display size, and frame frequency can be obtained by adjusting the external-resistor value. Internal resistors
can be used for R-C oscillation. If this is done, care must be taken due to variations in the oscillation
frequency caused by fluctuations in internal-resistor values. Clock pulses can also be supplied externally.
Since R-C oscillation stops during the standby mode, current consumption can be reduced. For details, see
the Oscillation Circuit section.
Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of 26 common signal drivers (COM1 to COM24, COMS1,
COMS2) and 72 (96) segment signal drivers (SEG1 to SEG72 (96)). When the number of lines are selected
by a program, the required common signal drivers automatically output drive waveforms, while the other
common signal drivers continue to output deselection waveforms.
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