HD66724 Datasheet, PDF (105/117 Pages) Hitachi Semiconductor – (Graphics LCD Controller/Driver with Key Scan Function)

HD66724/HD66725
Clock-Synchronized Serial Interface Timing Characteristics (V_CC = 1.8 to 5.5 V)
(V_CC = 1.8 to 2.7 V)
Item
Serial clock cycle time
Serial clock high-level width
Serial clock low-level width
Serial clock rise/fall time
Chip select set-up time
Chip select hold time
Serial input data set-up time
Serial input data hold time
Serial output data delay time
Serial output hold time
Write
Read
Write
Read
Write
Read
Symbol
t _SCYC
t _SCYC
t _SCH
t _SCH
t _SCL
t _SCL
t_SCf, t_SCr
t _CSU
t _CH
t _SISU
t _SIH
t _SOD
t _SOH
Min Typ Max Unit Test Condition
0.5 —
20
µs Figure 67
1
—
20
µs Figure 67
230 —
—
ns Figure 67
480 —
—
ns Figure 67
230 —
—
ns Figure 67
480 —
—
ns Figure 67
—
—
20
ns Figure 67
60
—
—
ns Figure 67
200 —
—
ns Figure 67
100 —
—
ns Figure 67
100 —
—
ns Figure 67
—
400 ns Figure 67
5
—
—
ns Figure 67
(V_CC = 2.7 to 5.5 V)
Item
Serial clock cycle time
Serial clock high-level width
Serial clock low-level width
Serial clock rise/fall time
Chip select setup time
Chip select hold time
Serial input data set-up time
Serial input data hold time
Serial output data delay time
Serial output hold time
Write
Read
Write
Read
Write
Read
Symbol
t _SCYC
t _SCYC
t _SCH
t _SCH
t _SCL
t _SCL
t_SCf, t_SCr
t _CSU
t _CH
t _SISU
t _SIH
t _SOD
t _SOH
Min Typ Max Unit Test Condition
0.2 —
20
µs Figure 67
0.5 —
20
µs Figure 67
80
—
—
ns Figure 67
230 —
—
ns Figure 67
80
—
—
ns Figure 67
230 —
—
ns Figure 67
—
—
20
ns Figure 67
60
—
—
ns Figure 67
200 —
—
ns Figure 67
40
—
—
ns Figure 67
40
—
—
ns Figure 67
—
200 ns Figure 67
5
—
—
ns Figure 67
105