HD66724 Datasheet, PDF (115/117 Pages) Hitachi Semiconductor – (Graphics LCD Controller/Driver with Key Scan Function)

80-System Bus Operation
HD66724/HD66725
RS
CS*
VIH
VIL
tAS
VIH
VIL
tAH
WR*
RD*
DB0
to DB7
DB0
to DB7
PWLR, PWLD
PWHR, PWHD
VIH
VIH
VIH
tWRr
VIL
VIL
tWRf
tCYCW, tCYCR
tDSW
tHWR
VIH
VIL
Write data
VIH
VIL
tDDR
tDHRD
VOH1
VOL1
Read data
VOH1
VOL1
Note: PWLW and PWLR is defined as the overlapped period of the low of CS* and the low of WR*/RD*.
Figure 66 80-System Bus Timing
Clock-Synchronized Serial Operation
CS*
SCL
SDA
SDA
Start: S
END: P
VIL
tCSU
VIH
VIL
VIL
tSCYC
tscr
tSCH ^tscf tCWL
tCH
VIH VIH
VIL
VIL
VIH
VIL
tSISU
tSIH
VIH
VIH
Input data
VIL
VIL
tSOD
Input data
tSOH
VOH1
Output data
VOH1
VOH1
Output data
VOL1
Figure 67 Clock-synchronized Serial Interface Timing
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