HD66724 Datasheet, PDF (53/117 Pages) Hitachi Semiconductor – (Graphics LCD Controller/Driver with Key Scan Function)

HD66724/HD66725
Table 31 Instruction List (cont)
Register
Name
Code
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
Execu-
tion
Cycle ^*1
Horizontal scroll 0 0 0 1 0 1 1 SSE SE2 SE1 Specifies SE1-4 bit selection 0
control 1
SE4 SE3 ^{(SSE) and the display line}
where horizontal scroll is
applied (SE1-4).
Horizontal scroll 0 0 0 1 1 0 0 SQ2 SQ1 SQ0 Specifies the amount of
0
control 2
scroll dot shift (SQ2-0) in
horizontal smooth scroll.
Key scan control 0 0 0 1 1 0 1 IRE KF1 KF0 Sets the key scan interrupt 0
(IRE) and key scan cycle
(KF1/0).
Port control
0 0 0 1 1 1 0 PT2 PT1 PT0 Sets the general port output 0
(PT2-0).
RAM address set 0 0 1 0 RM1 RM0
(upper bits)
AD9-6
(upper bits)
Sets the RAM selection
0
(RM1/0) and initial higher
RAM address to the address
counter (AC).
RAM address set 0 0 1 1
(lower bits)
AD5-0
(lower bits)
Sets the initial higher RAM 0
address to the address
counter (AC).
Write data 0 1
to RAM
Write data
Writes data to DDRAM,
0
CGRAM, or SEGRAM.
Read data from 1 1
RAM
Read data
Reads data from DDRAM, 0
CGRAM, or SEGRAM.
Note: 1. Represented by the number of operating clock pulses; the execution time depends on the
supplied clock frequency or the internal oscillation frequency.
Bit definition:
CMC = 0: COM1/24 => COM1
SGS = 0: SEG1/72 => SEG1
AMP = 1: Operational amplifier and booster circuit on
SLP = 1: Sleep mode
STB = 1: Standby mode
SW = 0: CT4-0 access/SW = 1: BT1/0 and BS2-0 access
CT4-0: Contrast adjustment
BT1/0: Boost level selection (00: Single, 01: Double, 10: Triple)
BS2-0: LCD drive bias selection
ROM = 0: CGROM bank 0 selection/ROM = 1: CGROM bank 1 selection
ID = 1: Address increment
ID = 0: Address decrement
GR = 1: Graphics display mode
GR = 0: Character display mode
B/W = 1: Black-white inverting cursor on
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