DS07-16301-4E Datasheet, PDF (85/99 Pages) Fujitsu Component Limited. – 32-bit RISC Microcontroller CMOS FR30 Series

MB91101/MB91101A
(11) Hyper DRAM Timing
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Parameter
Symbol
Pin name
Condition
Value
Min
Max
Unit Remarks
RAS delay time
tCLRAH3
tCHRAL3
CLK, RAS0, RAS1
CLK, RAS0, RAS1
—
6
ns
—
6
ns
CAS delay time
tCHCASL3
tCHCASH3
CLK, CS0H, CS0L,
CS1H, CS1L
CLK, CS0H, CS0L,
CS1H, CS1L
—
n/2 × tCYC ns
—
6
ns
ROW address delay time
tCHRAV3
CLK,
A24 to A00
—
15
ns
COLUMN address delay
time
tCHCAV3
CLK,
A24 to A00
—
15
ns
RD delay time
tCHRL3
tCHRH3
CLK, RD
CLK, RD
—
—
15
ns
—
15
ns
tCLRL3
CLK, RD
—
15
ns
DW delay time
tCHDWL3
tCHDWH3
CLK, DW0, DW1
CLK, DW0, DW1
—
15
ns
—
15
ns
Output data delay time
tCHDV3
CLK,
D31 to D16
—
15
ns
CAS ↓→ valid data input
time
tCLDV3
CS0H, CS0L, CS1H,
CS1L, D31 to D16
—
tCYC – 17 ns
CAS ↓→ data hold time
tCADH3
CS0H, CS0L, CS1H,
CS1L, D31 to D16
0
—
ns
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
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