DS07-16301-4E Datasheet, PDF (7/99 Pages) Fujitsu Component Limited. – 32-bit RISC Microcontroller CMOS FR30 Series

MB91101/MB91101A
Pin no.
LQFP*¹ QFP*²
11
14
10
13
9
12
8
11
7
10
6
9
5
8
96
99
97
100
98
1
99
2
100
3
*1: FPT-100P-M05
*2: FPT-100P-M06
Pin name
CS0
CS1
PA1
CS2
PA2
CS3
PA3
EOP1
CS4
PA4
CS5
PA5
CLK
PA6
RAS0
PB0
CS0L
PB1
CS0H
PB2
DW0
PB3
RAS1
PB4
EOP2
Circuit
type
Description
L Chip select 0 output (“L” active)
Chip select 1 output (“L” active)
F
Can be configured as a port when CS1 is not used.
Chip select 2 output (“L” active)
F
Can be configured as a port when CS2 is not used.
Chip select 3 output (“L” active)
Can be configured as a port when CS3 and EOP1 are not used.
F _{EOP output pin for DMAC (ch. 1)}
This function is available when EOP output for DMAC is en-
abled.
Chip select 4 output (“L” active)
F
Can be configured as a port when CS4 is not used.
Chip select 5 output (“L” active)
F
Can be configured as a port when CS5 is not used.
System clock output
F ^{Outputs clock signal of external bus operating frequency.}
Can be configured as a port when CLK is not used.
RAS output for DRAM bank 0
F ^{Refer to the DRAM interface for details.}
Can be configured as a port when RAS0 is not used.
CASL output for DRAM bank 0
F ^{Refer to the DRAM interface for details.}
Can be configured as a port when CS0L is not used.
CASH output for DRAM bank 0
F ^{Refer to the DRAM interface for details.}
Can be configured as a port when CS0H is not used.
WE output for DRAM bank 0 (“L” active)
F ^{Refer to the DRAM interface for details.}
Can be configured as a port when DW0 is not used.
RAS output for DRAM bank 1
Refer to the DRAM interface for details.
F
Can be configured as a port when RAS1 and EOP2 are not
used.
DMAC EOP output (ch. 2)
This function is available when DMAC EOP output is enabled.
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