DS07-16301-4E Datasheet, PDF (70/99 Pages) Fujitsu Component Limited. – 32-bit RISC Microcontroller CMOS FR30 Series

MB91101/MB91101A
(2) Clock Output Timing
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Parameter
Symbol Pin name Condition
Value
Min
Max
Unit Remarks
Cycle time
tCYC
CLK
—
tCP
tCYC
CLK
Using the
doubler
tCPB
—
ns *1
—
ns
CLK ↑ → CLK ↓
CLK ↓ → CLK ↑
tCHCL
tCLCH
CLK
CLK
1/2 × tCYC – 10 1/2 × tCYC + 10 ns *2
—
1/2 × tCYC – 10 1/2 × tCYC + 10 ns *3
tCP, tCPB (internal operating clock cycle time): Refer to “(1) Clock Timing Rating.”
*1: tCYC is a frequency for 1 clock cycle including a gear cycle.
Use the doubler when CPU frequency is above 25 MHz.
*2: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,
respectively.
Min : (1 – n/2) × tCYC – 10
Max : (1 – n/2) × tCYC + 10
Select a gear cycle of × 1 when using the doubler.
*3: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,
respectively.
Min : n/2 × tCYC – 10
Max : n/2 × tCYC + 10
Select a gear cycle of × 1 when using the doubler.
CLK
tCHCL
VOH
tCYC
tCLCH
VOL
VOH
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