DS07-16301-4E Datasheet, PDF (56/99 Pages) Fujitsu Component Limited. – 32-bit RISC Microcontroller CMOS FR30 Series

MB91101/MB91101A
12. Clock Generation (Low-power consumption mechanism)
The clock control block is a module which undertakes the following functions.
• CPU clock generation (including gear function)
• Peripheral clock generation (including gear function)
• Reset generation and cause hold
• Standby function (including hardware standby)
• DMA request prohibit
• PLL (multiplier circuit) embedded
• Block diagram
[Gear control block]
Gear control register (GCR)
X0
Oscillator
X1
circuit
PCTR register
PLL
1/2
CPU gear
Peripheral
gear
Internal clock
generation
circuit
Internal
interrupt request
Internal reset
CPU hold enable
HST pin
DMA
request
Power on sel
[Stop/sleep control block]
Standby control
register (STCR)
Status
transition
control circuit
[DMA prohibit circuit]
DMA request prohibit
register (PDRR)
[Reset cause circuit]
Reset
generation
F/F
CPU clock
Internal bus clock
External bus clock
Peripheral
DMA clock
Internal
peripheral clock
STOP state
SLEEP state
CPU hold request
Internal reset
RST pin
Reset cause register (RSRR)
[Watchdog control block]
Watchdog reset generation
postpone register (WPR)
Timebase timer clear
register (CTBR)
Watchdog reset
postpone register
Timebase timer
Count clock
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