DS07-16301-4E Datasheet, PDF (75/99 Pages) Fujitsu Component Limited. – 32-bit RISC Microcontroller CMOS FR30 Series

MB91101/MB91101A
(5) Normal Bus Access Read/Write Operation
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)
Parameter
Value
Symbol Pin name Condition
Unit Remarks
Min
Max
CS0 to CS5 delay time
tCHCSL
tCHCSH
CLK,
CS0 to CS5
CLK,
CS0 to CS5
—
15
ns
—
15
ns
Address delay time
tCHAV
CLK,
A24 to A00
—
15
ns
Data delay time
tCHDV
CLK,
D31 to D16
—
15
ns
RD delay time
tCLRL
tCLRH
CLK, RD
CLK, RD
—
6
ns
—
6
ns
tCLWL
CLK,
WR0, WR1
—
—
6
ns
WR0, WR1 delay time
tCLWH
CLK,
WR0, WR1
—
6
ns
Valid address → valid data
input time
tAVDV
A24 to A00,
D31 to D16
—
3/2 × tCYC
– 25
ns
*1
*2
RD ↓→ valid data input time tRLDV
RD,
D31 to D16
—
tCYC – 10 ns *1
Data set up → RD ↑ time
tDSRH
RD,
D31 to D16
10
—
ns
RD ↑→ data hold time
tRHDX
RD,
D31 to D16
0
—
ns
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
*1:When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC × extended cycle number for
delay) to this rating.
*2: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,
respectively.
Equation: (2 – n/2) × tCYC – 25
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