DS07-16301-4E Datasheet, PDF (52/99 Pages) Fujitsu Component Limited. – 32-bit RISC Microcontroller CMOS FR30 Series

MB91101/MB91101A
9. Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.
• Block diagram
NMI
RI00 *⁷
•
•
•
RI47 ^*7
(DLYIRQ)
INT0*²
OR
•
•
•
DLYI*¹
IM*⁶
Priority judgment
5
NMI processing
4
Level judgment
ICR00
• _{Vector judgment}
•
Level
vector
generation
6
ICR47
5
HLDREQ
cancel
request
LEVEL4 to
LEVEL0*⁴
HLDCAN*³
6
VCT5 to
VCT0*⁵
R-bus
*1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section “11.
Delayed Interrupt Module” for detail).
*2: INT0 is a wake-up signal to clock control block in the sleep or stop status.
*3: HLDCAN is a bus release request signal for bus masters other than CPU.
*4: LEVEL4 to LEVEL0 are interrupt level outputs.
*5: VCT5 to VCT0 are interrupt vector outputs.
*6: IM is an interrupt mask signal.
*7: RI00 to RI47 are interrupt request signals.
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