MB81EDS516545_10 Datasheet, PDF (6/60 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516545
10. Write Data Strobe (WDQS0 to WDQS3)
WDQS is input signal transmitted by the memory controller during write operation. WDQS is center aligned with
input data. WDQS0, WDQS1, WDQS2 and WDQS3 correspond to DQ[15:0], DQ[31:16], DQ[47:32] and
DQ[63:48] respectively. Refer to the “DQ/RDQS/WDQS/DM Correspondence Table”.
• DQ/RDQS/WDQS/DM Correspondence Table
DQ
RDQS
DQ[7:0]
DQ[15:8]
DQ[23:16]
DQ[31:24]
DQ[39:32]
DQ[47:40]
DQ[55:48]
DQ[63:56]
RDQS0
RDQS1
RDQS2
RDQS3
WDQS
WDQS0
WDQS1
WDQS2
WDQS3
DM
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
11. Select Area Enable (SA)
SA is used to support optional commands of MACT, MPRE and BREF. Refer to the “■COMMAND TRUTH
TABLE”. SA can be tied to VSS if optional commands are not required.
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DS05-11463-2E