MB81EDS516545_10 Datasheet, PDF (21/60 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516545
Minimum clock latency or delay time for multi bank operation
2nd Command (other bank)
MRS
tMRD
tMRD
⎯
⎯
⎯
⎯
tMRD
tMRD
tMRD
tMRD
tMRD
tMRD
tMRD
tMRD
⎯
ACT
⎯
tRRD
1
1
1
1
1
1
tRAS
⎯
⎯
tRRD
1
tRRD
*7
tRRD
*5
*5
READ ⎯
*1, *3
1
1
1
BL/2 BL/2
1
+CL +CL
1
*4
1
⎯
⎯
*1, *3
1
1
1
*7
1
*1, *2
READA ^BL/2
+ tRP
*1, *3
1
BL/2
BL/2
*5
BL/2
+CL
*5
BL/2
+CL
BL/2
+ tRP
1
*4
*1
*1
BL/2
+ tRP
BL/2
+ tRP
BL/2
+ tRP
*1, *3
1
1
1
*7
1
*4
*5
*5
WRIT
⎯
*1, *3
1
2
+ tWTR
2
+ tWTR
1
1
1
1
BL/2
+1
⎯
⎯
*1, *3
1
1
+ tWR
1
*7
1
*1
WRITA
BL/2
+1
*1, *3
1
*5
BL/2
+1
*5
BL/2
+1
BL/2
BL/2
BL/2
+1
1
*4
*1
*1
BL/2 BL/2 BL/2
*1, *3
+1
+1
+1
1
1
1
*7
1
+ tDAL
+ tWTR + tWTR
+ tDAL
+ tDAL
+ tDAL
+ tDAL
READ -
BST
⎯
1
1
CL
CL
1
*4
1
⎯
⎯
WRIT -
BST
⎯
*1, *3
1
1
+ tWTR
1
+ tWTR
1
1
1
*1, *3
1
1
*4
1
1
⎯
⎯
+ tWR
1
*7
1
PRE
*1, *2
tRP
*1, *3
1
1
1
1
1
1
1
1
*1
*1, *2
*1, *3
tRP
tRP
1
1
1
*7
1
PALL
*1
tRP
tRP
⎯
⎯
⎯
⎯
tRP
1
1
tRP
tRP
tRP
1
tRP
⎯
REF
tREFC
tREFC
⎯
⎯
⎯
⎯
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
⎯
SELFX tREFC
tREFC
⎯
⎯
⎯
⎯
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
⎯
MACT ⎯
tRRD
*6
1
*6
1
*6
1
*6
1
1
1
1+ tRAS
⎯
⎯
tRRD
1
tRRD
*7
tRRD
MPRE
*1, *2
tRP
*1, *3
1
1
1
1
1
1
1
1
*1
*1, *2
*1, *3
tRP
tRP
1
1
1
*7
1
BREF
RC x
tREFC
tRRD
1
1
1
1
1
1
RC x
tREFC
RC x
tREFC
RC x
tREFC
tRRD
1
RC x
tREFC
*7
tREFC
BREFX tREFC
tRRD
1
1
1
1
1
1
tREFC
tREFC
tREFC
tRRD
1
tREFC
⎯
“ - ” : illegal
*1: Assume other bank is in IDLE state.
*2: Assume output is in High-Z state.
*3: Assume tRRD is satisfied.
*4: Assume tRAS is satisfied.
*5: Assume appropriate DM masking.
*6: 1st read or write access must be allowed for appropriate bank specified in the ACT and MACT commands of
“■COMMAND TRUTH TABLE”.
*7: BREFX command can be issued only when Background Refresh is in progress.
DS05-11463-2E
21