MB81EDS516545_10 Datasheet, PDF (12/60 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516545
4. CAS Latency (CL)
CAS Latency (CL) is the delay between READ command being registered and first read data becoming available
during read operation. First read data will be valid after (CL-1) × tCK + tAC from the CK rising edge where Read
command being latched.
5. Driver Strength (DS)
Driver Strength (DS) is to adjust the driver strength of data output.
6. Pre Driver Strength (PDS)
Pre Driver Strength (PDS) is to adjust the transition time of the data output without changing the output driver
impedance.
7. Additional RDQS Toggle (ART)
Additional RDQS Toggle (ART) is to set RDQS toggle count after the last pair of data output. Total RDQS toggle
count is BL/2 + ART.
RDQS Timing with Additional RDQS Toggle (ART) function @BL=4
CK
CK
RDQS
ART = 0
RDQS
RDQS
RDQS
DQ
(Output)
Q0 Q1 Q2 Q3
ART = 1
1 additional RDQS toggle
ART = 2
2 additional RDQS toggles
ART = 3
3 additional RDQS toggles
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DS05-11463-2E