MB81EDS516545_10 Datasheet, PDF (4/60 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516545
1. Clock Inputs (CK and CK)
CK and CK are differential clock inputs. All address and control input signals are sampled on the rising edge of
CK. And the rising edge of CK and the rising edge of CK increment device internal address counter and drive
even and odd data input/out respectively.
tCK
CK
tCH
tCL
tCK
CK
tDC
tDC
tCH
tCL
2. Clock Enable (CKE)
CKE is a high active clock enable signal. When CKE = Low is latched at the rising edge of CK, the next CK rising
edge will be invalid. CKE controls power down mode and self refresh mode.
CK
CK
tIS
tIS
CKE
CK
(Internal)
3. Chip Select (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address inputs. CS = High disable command input
but internal operation such as burst cycle will not be suspended.
4. Command Inputs (RAS, CAS and WE)
The combination of RAS, CAS, and WE input in conjunction with CS at a rising edge of the CK define the
command for device operation. Refer to the “■COMMAND TRUTH TABLE”.
5. Bank Address Inputs (BA0, BA1)
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied.
4
DS05-11463-2E