MB81EDS516545_10 Datasheet, PDF (22/60 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516545
■ COMMAND DESCRIPTION
1. DESELECT (DESL)
When CS is High at the CK rising edge, all input signals are neglected. Internal operation such as burst cycle is
held.
2. NO OPERATION (NOP)
NOP disables address and data input and internal operation such as burst cycle is held.
3. BANK ACTIVE (ACT)
ACT activates the bank selected by BA and latch the row address through A0 to A12.
4. READ (READ)
READ initiates burst read operation to an activated row address. Address inputs of A[7:0] determine starting
column address and A10 determines whether Auto Precharge is used or not. Initially RDQS output Low level
then start toggling together with data output with respect to CL and BL. The read data output is edge-aligned
with first rising edge of RDQS and successive read data output are edge-aligned to the successive edge of
RDQS. The CK drives the rising edge of RDQS and Even data, and the CK drives the falling edge of RDQS and
Odd data.
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DS05-11463-2E