MB81EDS516545_10 Datasheet, PDF (35/60 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516545
(Continued)
Parameter
(Under recommended operating conditions unless otherwise noted)^{*1, *2}
Value
Symbol
Unit
Min.
Max.
ACT to PRE, MPRE, PALL Command Period *⁷
tRAS
37
8000
ns
ACT, MACT to ACT, MACT Command Period (Same Bank) *⁷
tRC
59.2
⎯
ns
REF to ACT, REF Command Period
tREFC
100
⎯
ns
ACT to READ or WRIT Command Period
tRCD
20
⎯
ns
Precharge Period *⁷
tRP
18
⎯
ns
ACT, MACT to ACT, MACT Command Period (Other Bank)*⁸ tRRD
9.2
⎯
ns
Write Recovery Time
tWR
12
⎯
ns
CL = 2
1 CLK + tRP
Data Input to ACT, REF Command Period
CL = 3
tDAL
2 CLK + tRP
⎯
ns
CL = 4
3 CLK + tRP
Internal Write to READ Command Delay
tWTR
9.2
⎯
ns
Average Refresh Period *⁹
Tj ≤ + 105°C
7.8
tREFI
⎯
μs
Tj ≤ + 125°C
2.0
Average Periodic Refresh Interval
Tj ≤ + 105°C
tREF
Tj ≤ + 125°C
64
⎯
ms
16.7
Transition Time*¹⁰
tT
⎯
1
ns
* 1: AC characteristics are measured after the Power up initialization procedure.
* 2: VDD × 0.5 is the reference level for 1.8 V I/O for measuring timing of input/output signals.
* 3: If input signal transition time (tT) is longer than 1 ns; [(tT/2) − 0.5] ns should be added to tAC (Max), tDQSCK (Max)
and tHZ (max) spec values, [(tT/2) − 0.5] ns should be subtracted from tLZ (Min) and tQH (Min) spec values, and
(tT - 1.0) ns should be added to tCH (Min), tCL (Min), tIS (Min), tIH (Min), tDS (Min) and tDH (Min) spec values.
* 4: The data valid window is defined as tQH - tDQSQ. The data valid window depends on tDC which is defined between
rising edge of CK and rising edge of CK. The data valid window is guaranteed when tDC is satisfied.
* 5: tAC, tDQSCK, tLZ and tHZ, are measured under output load circuit shown in “ 3. Measurement Condition of AC
Characteristics” in “ ■ ELECRTRICAL CHARACTERISTICS” and Driver Strength (DS) = Normal, Pre Driver
Strength (PDS) = Fast are assumed.
* 6: Specified where output buffer is no longer driven.
* 7: The sum of actual clock count of tRAS and tRP must be equal or greater than specified minimum tRC.
* 8: tRRD is applied to ACT (MACT) to BREF, ACT (MACT) to BREFX, BREF to ACT (MACT) and BREFX to ACT
(MACT). Refer to the “■ BANK OPERATION COMMAND TABLE”.
* 9: This value is for reference only.
* 10: Transition times are measured between VIH (AC) min and VIL (AC) max.
DS05-11463-2E
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