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| MB81EDS516545_10 Datasheet, PDF (57/60 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP | |||
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MB81EDS516545
(21) Multi Bank Active to Write to Multi Bank Precharge*1 (Assuming CL = 4, BL = 4)
CK
CK
CS
RAS
CAS
WE
BA
0
2
0
1
2
3
0
2
AP
RA
RA
Address
RA
RA
CA
CA
CA
CA
SA
DM
RDQS
WDQS
DQ
D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3
tRAS
tRCD
*2
*2
tWR
tRAS
tRRD
tRCD
*3
*3
tWR
MACT *2
MACT *3
Bank 0 & 1 Bank 2 & 3
WRIT *2
Bank 0
WRIT *2
Bank 1
WRIT *3
Bank 2
WRIT *3
Bank 3
MPRE
Bank 0 & 1
MPRE
Bank 2 & 3
Donât care
*1: RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge
*2: If MACT command is issued to Bank 0, 1st WRIT command must be issued to Bank 0 followed by 2nd WRIT
command to Bank 1.
*3: If MACT command is issued to Bank 2, 1st WRIT command must be issued to Bank 2 followed by 2nd WRIT
command to Bank 3.
DS05-11463-2E
57
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