MB81EDS516545_10 Datasheet, PDF (28/60 Pages) Fujitsu Component Limited. – 512M Bit (4 bank x 2M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS516545
20. MULTI BANK PRECHARGE (MPRE)
MULTI BANK PRECHARGE (MPRE) command starts precharge operation for 2 banks selected by BA1. SA
must be High to issue MPRE command. Selected 2 banks will be in IDLE state after specified time duration of tRP
from MPRE command. BA1 determines whether the target bank group is Bank 0 & 1 or Bank 2 & 3. If MPRE
command is issued to BA1 = L, Bank 0 and Bank 1 will be precharged simultaneously. If MPRE command is
issued to BA1 = H, Bank 2 and Bank 3 will be precharged simultaneously.
Command Truth Table of PRE, PALL and MPRE
Command
Symbol
CS
RAS CAS
WE
BA1
BA0
A10
(AP)
A[9:0],
A11, A12
SA
Precharged Bank
LL
Bank 0
PRECHARGE
SINGLE BANK
PRE
LH
L
HL
L
L LHLHH
X
PRECHARGE
ALL BANK
PALL
XXH
Bank 1
Bank 2
Bank 3
All Banks
MULTI BANK
PRECHARGE
MPRE
L
XL
H
Bank 0 & 1
H
Bank 2 & 3
21. BACKGROUND REFRESH ENTRY (BREF)
BACKGROUND REFRESH ENTRY (BREF) command starts internal refresh operation for 2 banks selected by
BA1. SA must be High to issue BREF command and A10 determines either BACKGROUND REFRESH ENTRY
(BREF) or EXIT (BREFX). 2 banks which will be refreshed must be precharged prior to the BREF command.
When BREF command is issued, Refresh Count (RC) must be set through A[9:0] inputs as shown in the following
table. RC defines how many refresh cycle is executed by one BREF command. RC can be set from 1 to 31
cycles. Refreshed banks will be in REFRESH state for a period specified by RC x tREFC. While any read and write
access must not be performed during AUTO REFRESH which initiates all banks refresh, background refresh can
allow to read or write access to 2 banks which are not refreshed. BA1 determines the target bank group either
Bank 0 & 1 or Bank 2 & 3. If BREF command is issued to BA1 = L, Bank 0 & 1 will be refreshed and Bank 2 &
3 can be accessible. If BREF command is issued to BA1 = H, Bank 2 & 3 will be refreshed and Bank 0 & 1 can
be accessible. 8,192 BREF command must be asserted to both bank group of Bank 0 & 1 and Bank 2 & 3 within
the refresh period of tREF. When background refresh is in progress for one bank group, BREF command must
not be issue to the other bank group.
22. BACKGROUND REFRESH EXIT (BREFX)
BACKGROUND REFRESH EXIT (BREFX) command terminates internal refresh operation for 2 banks initiated
by BREF command for a period of RC x tREFC. SA must be High to issue BREFX command. 2 banks will be IDLE
state after tREFC from BREFX command. BREFX command can be issued when background refresh is in progress.
28
DS05-11463-2E