MB85RS2MTPF-G Datasheet, PDF (2/28 Pages) Fujitsu Component Limited. – 2 M (256 K × 8) Bit SPI

MB85RS2MT
■ PIN ASSIGNMENT
(TOP VIEW)
(TOP VIEW)
CS
SO
WP
VSS
1
8
2
7
3
6
4
5
(DIP-8P-M03)
VDD
CS
HOLD
SO
SCK _WP
SI
VSS
1
8
2
7
3
6
4
5
(FPT-8P-M08)
VDD
HOLD
SCK
SI
■ PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
Functional description
Chip Select pin
This is an input pin to make chips select. When CS is “H” level, device is in deselect
1
CS (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this
time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before
inputting op-code.
Write Protect pin
3
WP
This is a pin to control writing to a status register. The writing of status register (see “■
STATUS REGISTER”) is protected in related with WP and WPEN. See “■ WRITING
PROTECT” for detail.
Hold pin
7
HOLD
This pin is used to interrupt serial input/output without making chips deselect. When
HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become
do not care. While the hold operation, CS has to be retained “L” level.
Serial Clock pin
6
SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
5
SI
Serial Data Input pin
This is an input pin of serial data. This inputs op-code, address, and writing data.
Serial Data Output pin
2
SO This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
8
VDD Supply Voltage pin
4
VSS Ground pin
2
DS501-00023-0v01-E