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MB85RS2MTPF-G Datasheet, PDF (12/28 Pages) Fujitsu Component Limited. – 2 M (256 K × 8) Bit SPI | |||
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MB85RS2MT
â BLOCK PROTECT
Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register.
BP1
BP0
Protected Block
0
0
None
0
1
30000H to 3FFFFH (upper 1/4)
1
0
20000H to 3FFFFH (upper 1/2)
1
1
00000H to 3FFFFH (all)
â WRITING PROTECT
Writing operation of the WRITE command and the WRSR command are protected with the value of WEL,
WPEN, WP as shown in the table.
WEL
WPEN
WP
Protected Blocks Unprotected Blocks
Status Register
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
â HOLD OPERATION
Hold status is retained without aborting a command if HOLD is âLâ level while CS is âLâ level. The timing for
starting and ending hold status depends on the SCK to be âHâ level or âLâ level when a HOLD pin input is
transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to âLâ level
when SCK is âLâ level, return the HOLD pin to âHâ level at SCK being âLâ level. In the same manner, in case
the HOLD pin transited to âLâ level when SCK is âHâ level, return the HOLD pin to âHâ level at SCK being âHâ
level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become do not care.
And, SO becomes High-Z while reading command (RDSR, READ). If CS is rising during hold status, a
command is aborted. In case the command is aborted before its recognition, WEL holds the value before
transition to hold status.
CS
SCK
HOLD
Hold Condition
Hold Condition
12
DS501-00023-0v01-E
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