MB85RS2MTPF-G Datasheet, PDF (10/28 Pages) Fujitsu Component Limited. – 2 M (256 K × 8) Bit SPI

MB85RS2MT
• FSTRD
The FSTRD command reads FRAM memory cell array data. Arbitrary 24 bits address and op-code of FSTRD
are input to SI followed by 8 bits dummy. The 6-bit upper address bit is invalid. Then, 8-cycle clock is input
to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When
CS is risen, the FSTRD command is completed, but keeps on reading with automatic address increment
which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches
the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. FSTRD
command is applicable to “Up to 25 MHz (1.8 V to 2.7 V) and 40 MHz (2.7 V to 3.6 V) operation”.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 29 30 31 32 33 38 39 40 41 42 43 44 45 46 47
SCK
OP-CODE
24-bit Address
8-bit Dummy
SI 0 0 0 0 1 0 1 1 X X X X X X 17 16 _{2 1 0 X X X X} Invalid
MSB
High-Z
LSB
MSB Data Out LSB
SO
76543210
Invalid
• RDID
The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to
SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output
is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte).
In the RDID command, SO holds the output state of the last bit after 32-bit Device ID output by continuously
sending SCK clock before CS is risen. RDID command is applicable to “Up to 25 MHz operation”.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11
31 32 33 34 35 36 37 38 39
SI
10011111
Invalid
SO ^High-Z
Data Out
31 30 29 28
MSB
Data Out
876543210
LSB
Manufacturer ID
Continuation code
bit
7654321
0000010
0111111
Proprietary use
Product ID (1st Byte) 0 0 1 0
Density
100
Proprietary use
Product ID (2nd Byte) 0 0 0 0 0 0 1
0 Hex
0 04H Fujitsu
1 7FH
Hex
0 28H Density: 01000B = 2 Mbit
Hex
1 03H
10
DS501-00023-0v01-E