PXS20 Datasheet, PDF (99/119 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Electrical characteristics
Table 30. Reset sequence trigger — reset sequence
Reset Sequence
Reset
Sequence
Trigger
All internal
destructive reset
sources
(LVDs or internal
HVD during
power-up and
during
operation)
Assertion of
RESET³
Reset
Sequence
Start
Condition
Section 3.1
9.4.1,
Destructive
reset
Section 3.1
9.4.2,
External
reset via
RESET
Reset
Sequence
End
Indication
Destructiv
e Reset
Sequence,
BIST
enabled¹
Destructiv
e Reset
Sequence,
BIST
disabled¹
External
Reset
Sequenc
e Long,
BIST
enabled
Release of
RESET²
triggers
cannot
trigger
cannot trigger
triggers⁴
Functiona
l Reset
Sequenc
e Long
Functiona
l Reset
Sequenc
e Short
cannot
trigger
cannot
trigger
triggers⁵ triggers⁶
All internal
functional reset
sources
configured for
long reset
Sequence
starts with
internal
reset
trigger
Release of
RESET⁷
cannot trigger
cannot
trigger
triggers
cannot
trigger
All internal
functional reset
sources
configured for
short reset
cannot trigger
cannot
trigger
cannot
trigger
triggers
1 _{Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM.}
2 _{End of the internal reset sequence (as specified in Table 29) can only be observed by release of RESET if it is not}
held low externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 till
RESET is released externally.
3 _{The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before.}
RESET does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST
disabled. However, it can prolong these sequences if RESET is held low externally beyond the end of the internal
sequence (beyond PHASE3).
4 _{If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the}
shadow sector of the NVM.
5 _{If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the}
shadow sector of the NVM.
6 _{If RESET is configured for short reset}
7 _{Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for}
the functional reset source which triggered the reset sequence.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
99
Preliminary—Subject to Change Without Notice