PXS20 Datasheet, PDF (98/119 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Electrical characteristics
Reset Sequence Trigger
Reset Sequence Start Condition
R_RES_EE_ST_E__TB
PHASE1,2
PHASE3
Flash init
Device
Config
T_{FRL, min} < T_Reset < T_{FRL, max}
DRUN
Application
Execution
Figure 16. Functional Reset Sequence Long
Reset Sequence Trigger
Reset Sequence Start Condition
R_RE_ES_SE_ET_T_B
PHASE3
T_{FRS, min} < T_Reset < T_{FRS, max}
DRUN
Application
Execution
Figure 17. Functional Reset Sequence Short
The reset sequences shown in Figure 16 and Figure 17 are triggered by functional reset events. RESET is driven low during
these two reset sequences only if the corresponding functional reset source (which triggered the reset sequence) was enabled to
drive RESET low for the duration of the internal reset sequence¹.
3.19.3 Reset sequence trigger mapping
The following table shows the possible trigger events for the different reset sequences. It specifies the reset sequence start
conditions as well as the reset sequence end indications that are the basis for the timing data provided in Table 29.
1.See RGM_FBRE register for more details.
PXS20 Microcontroller Data Sheet, Rev. 1
98
Preliminary—Subject to Change Without Notice
Freescale Semiconductor