PXS20 Datasheet, PDF (79/119 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Electrical characteristics
Table 14. ESD ratings^{1, 2}
No.
Symbol
Parameter
Conditions
Class Max value³ Unit
1
V_ESD(HBM) SR Electrostatic discharge T_A = 25 °C
H1C
2000
V
(Human Body Model) conforming to AEC-Q100-002
2
V_ESD(MM) SR Electrostatic discharge T_A = 25 °C
M2
200
V
(Machine Model)
conforming to AEC-Q100-003
3
V_ESD(CDM) SR Electrostatic discharge T_A = 25 °C
C3A
500
V
(Charged Device Model) conforming to AEC-Q100-011
750 (corners)
1 _{All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated}
Circuits.
2 _{A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device}
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
3 _{Data based on characterization results, not tested in production.}
3.7 Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 15. Latch-up results
No.
Symbol
Parameter
1
LU
SR Static latch-up class
Conditions
T_A = 125 °C conforming to JESD 78
Class
II level A
3.8 Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
• High power regulator HPREG1 (internal ballast to support core current)
• High power regulator HPREG2 (external NPN to support core current)
• Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (V_DDIO)
• Low voltage detector (LVD_MAIN_2) for 3.3 V supply (V_DDREG)
• Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (V_DDFLASH)
• Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPV_DD)
• Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN
• High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPV_DD)
• High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN.
• Power on Reset (POR)
HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when external NPN transistor is present on
board to supply core current. The PXS20 always powers up using HPREG1 if an external NPN transistor is present. Then the
PXS20 makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is fully operational, the
controller part of HPREG1 is switched off. The following bipolar transistors are supported:
• BCP68 from ON Semiconductor
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
79
Preliminary—Subject to Change Without Notice