PXS20 Datasheet, PDF (3/119 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

1 Introduction
Introduction
1.1 Document overview
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams for the PXS20 series of
microcontroller units (MCUs). For functional characteristics, see the PXS20 Microcontroller Reference Manual. For use of the
PXS20 in a fail-safe system according to safety standard IEC 61508, see the Safety Application Guide for MPC5643L.
The PXS20 MCU series is available in two silicon versions, or “cuts”. These are referred to as “cut1” and “cut2” throughout
this document. Functional differences between the two cuts are clearly identified with the labels “cut1” and “cut2”.
1.2 Description
The PXS20 series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain
enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital
signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital
converter, Controller Area Network, and an enhanced modular input-output system.
The PXS20 family of 32-bit microcontrollers is the latest achievement in integrated safety controllers. The advanced and
cost-efficient host processor core of the PXS20 family complies with the Power Architecture embedded category. It operates at
speeds as high as 120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the
available development infrastructure of current Power Architecture devices and is supported with software drivers, operating
systems and configuration code to assist with users’ implementations.
1.3 Device comparison
Table 1. PXS20 Family Feature Set
CPU
Buses
Type
Feature
Architecture
Execution speed
DMIPS intrinsic performance
SIMD (DSP + FPU)
MMU
Instruction set PPC
Instruction set VLE
Instruction cache
MPU-16 regions
Semaphore unit (SEMA4)
Core bus
Internal periphery bus
PXS20
2 × e200z4
(in lock-step or decoupled operation)
Harvard
0 – 120 MHz (+2% FM)
> 240 MIPS
Yes
16 entry
Yes
Yes
4 KB, EDC
Yes, replicated module
Yes
AHB, 32-bit address, 64-bit data
32-bit address, 32-bit data
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
3
Preliminary—Subject to Change Without Notice