PXS20 Datasheet, PDF (53/119 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Package pinouts and signal descriptions
Table 5. Supply pins (continued)
Supply
Symbol
Description
V_{DD_LV_COR}
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest V_{SS_LV_COR} pin.
V_SS 1V2
VSS_LV_PLL0_PLL1 /
1.2 V Decoupling pins for on-chip FMPLL modules. Decoupling capacitor
must be connected between this pin and V_{DD_LV_PLL.}
V_DD 1V2
VDD_LV_PLL0_PLL1
Decoupling pins for on-chip FMPLL modules. Decoupling capacitor must
be connected between this pin and V_{SS_LV_PLL.}
V_{DD_LV_COR}
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest V_{SS_LV_COR} pin.
V_{SS_LV_COR}
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest V_{DD_LV_COR} pin.
V_{DD_LV_COR}
VDD_LV_COR
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and V_{SS_LV_REGCOR.}
V_{SS_LV_COR}
VSS_LV_REGCOR0
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and V_{DD_LV_REGCOR.}
V_{DD_LV_COR}
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest V_{SS_LV_COR} pin.
V_{SS_LV_COR}
VSS_LV_COR
/ 1.2 V Decoupling pins for core logic. Decoupling capacitor must be
connected between these pins and the nearest V_{DD_LV_COR pin.}
V_DD 1V2
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest V_{DD_LV_COR} pin.
V_SS 1V2
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest V_{DD_LV_COR} pin.
V_DD 1V2
VDD_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest V_{DD_LV_COR} pin.
V_SS 1V2
VSS_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest V_{DD_LV_COR} pin.
1 _{VDD_LV balls are tied together on the 257 MAPBGA substrate.}
2 _{VSS_LV balls are tied together on the 257 MAPBGA substrate.}
3 _{VDD_HV balls are tied together on the 257 MAPBGA substrate.}
4 _{VSS_HV balls are tied together on the 257 MAPBGA substrate.}
Pin #
144 257
pkg pkg
18 VDD_LV¹
35
N4
36
P4
39 VDD_LV¹
40 VSS_LV²
70 VDD_LV¹
71 VSS_LV²
93 VDD_LV¹
94 VSS_LV²
131 VDD_LV¹
132 VSS_LV²
135 VDD_LV¹
137 VSS_LV²
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
53
Preliminary—Subject to Change Without Notice