PXS20 Datasheet, PDF (7/119 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Introduction
ADC
– Analog-to-digital converter
BAM
– Boot assist module
CAN
– Controller area network controller
CMU
– Clock monitoring unit
CRC
– Cyclic redundancy check unit
CTU
– Cross Triggering Unit
ECC
– Error correction code
ECSM – Error correction status module
eDMA – Enhanced direct memory access controller
FCCU – Fault collection and control unit
FMPLL – Frequency modulated phase locked loop
INTC
– Interrupt controller
IRCOSC – Internal RC oscillator
JTAG
– Joint Test Action Group interface
MC
– Mode entry, clock, reset, & power
PBRIDGE – Peripheral I/O bridge
PIT
– Periodic interrupt timer
PMU
– Power management unit
PWM
– Pulse width modulator module
RC
– Redundancy checker
RTC
– Real time clock
SEMA4 – Semaphore unit
SIUL
– System integration unit lite
SPI
– Serial peripherals interface controller
SSCM – System status and configuration module
STM
– System timer module
SWG
– Sine wave generator
SWT
– Software watchdog timer
TSENS – Temperature sensor
UART/LIN – Universal asynchronous receiver/transmitter/
local interconnect network
WKPU – Wakeup unit
XOSC – Crystal oscillator
Figure 2. PXS20 block diagram (continued)
1.5 Feature details
1.5.1 High-Performance e200z4d Core
The e200z4d Power Architecture^® core provides the following features:
• 2 independent execution units, both supporting fixed-point and floating-point operations
• Dual issue 32-bit Power Architecture^® technology compliant
— 5-stage pipeline (IF, DEC, EX1, EX2, WB)
— In-order execution and instruction retirement
• Full support for Power Architecture^® instruction set and Variable Length Encoding (VLE)
— Mix of classic 32-bit and 16-bit instruction allowed
— Optimization of code size possible
• Thirty-two 64-bit general purpose registers (GPRs)
• Harvard bus (32-bit address, 64-bit data)
— I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return
— D-Bus interface capable of two transactions outstanding to fill AHB pipe
• I-cache and I-cache controller
— 4 KB, 256-bit cache line (programmable for 2- or 4-way)
• No data cache
• 16-entry MMU
• 8-entry branch table buffer
• Branch look-ahead instruction buffer to accelerate branching
• Dedicated branch address calculator
• 3 cycles worst case for missed branch
• Load/store unit
— Fully pipelined
— Single-cycle load latency
— Big- and little-endian modes supported
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
7
Preliminary—Subject to Change Without Notice