PXS20 Datasheet, PDF (87/119 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Electrical characteristics
Table 21. FMPLL electrical characteristics (continued)
Symbol
Parameter
Conditions
Min Typ Max Unit
t_lpll
t_dc
C_JITTER
t_PKJIT
D FMPLL lock time ^{6, 7}
—
D Duty cycle of reference
—
T CLKOUT period jitter^8,9,10,11
Long-term jitter (avg. over 2 ms
interval), f_SYS maximum
T Single period jitter (peak to peak) PHI @ 120 MHz,
Input clock @ 4 MHz
—
— 200 s
40
—
60 %
–6
—
6 ns
—
— 175 ps
PHI @ 100 MHz,
Input clock @ 4 MHz
—
— 185 ps
t_LTJIT T Long term jitter
PHI @ 80 MHz,
Input clock @ 4 MHz
PHI @ 16 MHz,
Input clock @ 4 MHz
—
— 200 ps
—
—
±6 ns
f_LCK D Frequency LOCK range
—
–6
—
6%
f_sys
f_UL
D Frequency un-LOCK range
f_CS D Modulation Depth
f_DS
—
Center spread
Down Spread
–18
±0.25
–0.5
—
18 %
f_sys
— ±2.0¹² %
—
-8.0 ^fsys
f_MOD D Modulation frequency¹³
—
—
— 100 kHz
1 _{Considering operation with FMPLL not bypassed.}
2 _{With FM; the value does not include a possible +2% modulation}
3 _{“Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self}
clocked mode.
4 _{Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls}
outside the f_LOR window.
5 _{fVCO is the frequency at the output of the VCO; its range is 256–512 MHz.}
f_SCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz.
f_SYS = f_VCOODF
6 _{This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for}
this FMPLL, load capacitors should not exceed these limits.
7 _{This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control}
bits in the synthesizer control register (SYNCR).
8 _{This value is determined by the crystal manufacturer and board design.}
9 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum}
f_SYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the FMPLL circuitry via V_DDPLL and V_SSPLL and variation in crystal oscillator frequency
increase the C_JITTER percentage for a given interval.
10 _{Proper PC board layout procedures must be followed to achieve specifications.}
11 _{Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and}
either f_CS or f_DS (depending on whether center spread or down spread modulation is enabled).
12 _{This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).}
13 _{Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz.}
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
87
Preliminary—Subject to Change Without Notice