PXS20 Datasheet, PDF (12/119 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Introduction
For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can
be raised temporarily so that all tasks which share the resource can not preempt each other.
The INTC provides the following features:
• Duplicated periphery
• Unique 9-bit vector per interrupt source
• 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
• Priority elevation for shared resource
The INTC is replicated for each processor.
1.5.13 System Clocks and Clock Generation
The following list summarizes the system clock and clock generation on this device:
• Lock status continuously monitored by lock detect circuitry
• Loss-of-clock (LOC) detection for reference and feedback clocks
• On-chip loop filter (for improved electromagnetic interference performance and fewer external components required)
• Programmable output clock divider of system clock (1, 2, 4, 8)
• PWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock
(with max frequency 120 MHz)
• On-chip crystal oscillator with automatic level control
• Dedicated internal 16 MHz internal RC oscillator for rapid start-up
— Supports automated frequency trimming by hardware during device startup and by user application
• Auxiliary clock domain for motor control periphery (PWM, eTimer, CTU, ADC, and SWG)
1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL)
Each device has two FMPLLs.
Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock.
Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor,
output clock divider ratio are all software configurable. The FMPLLs have the following major features:
• Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)
• Voltage controlled oscillator (VCO) range: 256–512 MHz
• Frequency modulation via software control to reduce and control emission peaks
— Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register
— Modulation frequency: triangular modulation with 25 kHz nominal rate
• Option to switch modulation on and off via software interface
• Reduced frequency divider (RFD) for reduced frequency operation without re-lock
• 3 modes of operation
— Bypass mode
— Normal FMPLL mode with crystal reference (default)
— Normal FMPLL mode with external reference
• Lock monitor circuitry with lock status
PXS20 Microcontroller Data Sheet, Rev. 1
12
Freescale Semiconductor
Preliminary—Subject to Change Without Notice