MC68711E20CFNE3 Datasheet, PDF (98/242 Pages) –

Parallel Input/Output (I/O) Ports
6.2 Port A
Port A shares functions with the timer system and has:
• Three input-only pins
• Three output-only pins
• Two bidirectional I/O pins
Address: $1000
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Write:
Reset:
I
0
0
0
I
I
I
I
Alternate function: PAI
OC2
OC3
OC4 IC4/OC5 IC1
IC2
IC3
And/or: OC1
OC1
OC1
OC1
OC1
—
—
—
I = Indeterminate after reset
Figure 6-1. Port A Data Register (PORTA)
Address:
Read:
Write:
Reset:
$1026
Bit 7
DDRA7
0
6
PAEWN
0
5
PAMOD
0
4
PEDGE
0
3
DDRA3
0
2
I4/O5
0
1
RTR1
0
Bit 0
RTR0
0
Figure 6-2. Pulse Accumulator Control Register (PACTL)
DDRA7 — Data Direction for Port A Bit 7
Overridden if an output compare function is configured to control the PA7 pin
0 = Input
1 = Output
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also be used as
general-purpose I/O or as an output compare.
NOTE
Even when port A bit 7 is configured as an output, the pin still drives the
input to the pulse accumulator.
PAEN — Pulse Accumulator System Enable Bit
Refer to Chapter 9 Timing Systems.
PAMOD — Pulse Accumulator Mode Bit
Refer to Chapter 9 Timing Systems.
PEDGE — Pulse Accumulator Edge Control Bit
Refer to Chapter 9 Timing Systems.
DDRA3 — Data Direction for Port A Bit 3
This bit is overridden if an output compare function is configured to control the PA3 pin.
0 = Input
1 = Output
I4/O5 — Input Capture 4/Output Compare 5 Bit
Refer to Chapter 9 Timing Systems.
RTR[1:0] — RTI Interrupt Rate Select Bits
Refer to Chapter 9 Timing Systems.
M68HC11E Family Data Sheet, Rev. 5.1
98
Freescale Semiconductor