MC68711E20CFNE3 Datasheet, PDF (34/242 Pages) –

Operating Modes and On-Chip Memory
Addr.
$1000
$1001
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Port A Data Register ^Read: _PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
(PORTA) Write:
See page 98. _{Reset: I}
0
0
0
I
I
I
I
Reserved
R
R
R
R
R
R
R
R
$1002
$1003
$1004
$1005
$1006
Parallel I/O Control Register
(PIOC)
See page 102.
Read:
Write:
Reset:
Port C Data Register
(PORTC)
See page 99.
Read:
Write:
Reset:
Port B Data Register
(PORTB)
See page 99.
Read:
Write:
Reset:
Port C Latched Register
(PORTCL)
See page 99.
Read:
Write:
Reset:
Reserved
STAF
0
PC7
PB7
0
PCL7
R
STAI
0
PC6
PB6
0
PCL6
R
CWOM HNDS
OIN
PLS
0
0
0
U
PC5
PC4
PC3
PC2
Indeterminate after reset
PB5
PB4
PB3
PB2
0
0
0
0
PCL5
PCL4
PCL3
PCL2
Indeterminate after reset
R
R
R
R
EGA INVB
1
1
PC1
PC0
PB1
0
PCL1
PB0
0
PCL0
R
R
$1007
Port C Data Direction Register
(DDRC)
See page 100.
Read:
Write:
Reset:
DDRC7
0
DDRC6
0
DDRC5
0
$1008
Port D Data Register ^Read: ₀
(PORTD) Write:
See page 100. _{Reset: U}
0
PD5
U
I
Port D Data Direction Register ^Read:
$1009
(DDRD) Write:
See page 100. _{Reset: 0}
DDRD5
0
0
$100A
Port E Data Register ^Read: _PE7
PE6
PE5
(PORTE) Write:
See page 101. _Reset:
$100B
Timer Compare Force Register
(CFORC)
See page 135.
Read:
Write:
Reset:
FOC1
0
FOC2
0
FOC3
0
$100C
Output Compare 1 Mask Register
(OC1M)
See page 136.
Read:
Write:
Reset:
OC1M7
0
OC1M6
0
OC1M5
0
= Unimplemented
I = Indeterminate after reset
DDRC4 DDRC3 DDRC2 DDRC1
0
0
0
0
PD4
PD3
PD2
PD1
I
I
I
I
DDRD4 DDRD3 DDRD2 DDRD1
0
0
0
0
PE4
PE3
PE2
PE1
Indeterminate after reset
FOC4
FOC5
0
0
0
0
OC1M4 OC1M3
0
0
0
0
R = Reserved U = Unaffected
Figure 2-7. Register and Control Bit Assignments (Sheet 1 of 6)
DDRC0
0
PD0
I
DDRD0
0
PE0
0
0
M68HC11E Family Data Sheet, Rev. 5.1
34
Freescale Semiconductor