MC68711E20CFNE3 Datasheet, PDF (169/242 Pages) –

MC68L11E9/E20 Expansion Bus Timing Characteristics
10.16 MC68L11E9/E20 Expansion Bus Timing Characteristics
Num
Characteristic⁽¹⁾
1.0 MHz
Symbol
Min Max
2.0 MHz
Unit
Min Max
Frequency of operation (E-clock frequency)
1 Cycle time
2 Pulse width, E low, PW_EL = 1/2 t_CYC–25 ns
3 Pulse width, E high, PW_EH = 1/2 t_CYC–30 ns
4a E and AS rise time
4b E and AS fall time
9 Address hold time^{(2) (2)a}, t_AH = 1/8 t_CYC–30 ns
Non-multiplexed address valid time to E rise
12
t_AV = PW_EL –(t_ASD + 80 ns)^(2)a
17 Read data setup time
18 Read data hold time , max = t_MAD
19 Write data delay time, t_DDW = 1/8 t_CYC+ 70 ns^(2)a
21 Write data hold time, t_DHW = 1/8 t_CYC–30 ns^(2)a
Multiplexed address valid time to E rise
22
t_AVM = PW_EL –(t_ASD + 90 ns)^(2)a
Multiplexed address valid time to AS fall
24
t_ASL = PW_ASH –70 ns
25 Multiplexed address hold time, t_AHL = 1/8 t_CYC–30 ns^(2)b
26 Delay time, E to AS rise, t_ASD = 1/8 t_CYC–5 ns^(2)a
27 Pulse width, AS high, PW_ASH = 1/4 t_CYC–30 ns
28 Delay time, AS to E rise, t_ASED = 1/8 t_CYC–5 ns^(2)b
29
MPU address access time^(3)a
t_ACCA = t_CYC–(PW_EL–t_AVM) –t_DSR–t_f
35 MPU access time, t_ACCE = PW_EH –t_DSR
Multiplexed address delay (Previous cycle MPU read)
36
t_MAD = t_ASD + 30 ns^(2)a
f_o
dc
1.0
dc
2.0 MHz
t_CYC
1000
—
500
—
ns
PW_EL 475
—
225
—
ns
PW_EH 470
—
220
—
ns
t_r
—
25
—
25 ns
t_f
—
25
—
25 ns
t_AH
95
—
33
— ns
t_AV
275 —
88
— ns
t_DSR
t_DHR
t_DDW
t_DHW
30
—
30
0
150
0
— ns
88 ns
— 195 — 133 ns
95
—
33
— ns
t_AVM
268 —
78
— ns
t_ASL
150 —
25
— ns
t_AHL
95
—
33
— ns
t_ASD
120 —
58
— ns
PW_ASH 220
—
95
— ns
t_ASED
120
—
58
— ns
t_ACCA
735
—
298
—
ns
t_ACCE
—
440
— 190 ns
t_MAD
150
—
88
— ns
1. V_DD = 3.0 Vdc to 5.5 Vdc, V_SS = 0 Vdc, T_A = T_L to T_H, all timing is shown with respect to 20% V_DD and 70% V_DD, unless
otherwise noted
2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 t_CYCin the above formulas, where applicable:
(a) (1–dc) × 1/4 t_CYC
(b) dc × 1/4 t_CYC
Where:
dc is the decimal value of duty cycle percentage (high time).
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
169