MC68711E20CFNE3 Datasheet, PDF (141/242 Pages) –

Real-Time Interrupt (RTI)
independent of the software latencies associated with flag clearing and service. For this reason, an RTI
period starts from the previous timeout, not from when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is generated.
After reset, one entire RTI period elapses before the RTIF is set for the first time. Refer to the 9.4.9 Timer
Interrupt Mask 2 Register, 9.5.2 Timer Interrupt Flag Register 2, and 9.5.3 Pulse Accumulator Control
Register.
9.5.1 Timer Interrupt Mask Register 2
This register contains the real-time interrupt enable bits.
Address: $1024
Bit 7
6
5
4
3
Read:
TOI
Write:
RTI
PAOVI
PAII
Reset: 0
0
0
0
0
= Unimplemented
2
1
Bit 0
PR1
PR0
0
0
0
Figure 9-21. Timer Interrupt Mask 2 Register (TMSK2)
TOI — Timer Overflow Interrupt Enable Bit
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to 1
RTII — Real-Time Interrupt Enable Bit
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF set to 1
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
Refer to 9.7 Pulse Accumulator.
PAII — Pulse Accumulator Input Edge Bit
Refer to 9.7 Pulse Accumulator.
Bits [3:2] — Unimplemented
Always read 0
PR[1:0] — Timer Prescaler Select Bits
Refer to Table 9-4.
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2
enable the corresponding interrupt sources.
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
141