MC68711E20CFNE3 Datasheet, PDF (85/242 Pages) –

Reset and Interrupt Priority
5.3.9 Analog-to-Digital (A/D) Converter
The analog-to-digital (A/D) converter configuration is indeterminate after reset. The ADPU bit is cleared
by reset, which disables the A/D system. The conversion complete flag is indeterminate.
5.3.10 System
The EEPROM programming controls are disabled, so the memory system is configured for normal read
operation. PSEL[3:0] are initialized with the value %0110, causing the external IRQ pin to have the
highest I-bit interrupt priority. The IRQ pin is configured for level-sensitive operation (for wired-OR
systems). The RBOOT, SMOD, and MDA bits in the HPRIO register reflect the status of the MODB and
MODA inputs at the rising edge of reset. MODA and MODB inputs select one of the four operating modes.
After reset, writing SMOD and MDA in special modes causes the MCU to change operating modes. Refer
to the description of HPRIO register in Chapter 2 Operating Modes and On-Chip Memory for a detailed
description of SMOD and MDA. The DLY control bit is set to specify that an oscillator startup delay is
imposed upon recovery from stop mode. The clock monitor system is disabled because CME is cleared.
5.4 Reset and Interrupt Priority
Resets and interrupts have a hardware priority that determines which reset or interrupt is serviced first
when simultaneous requests occur. Any maskable interrupt can be given priority over other maskable
interrupts.
The first six interrupt sources are not maskable. The priority arrangement for these sources is:
1. POR or RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. XIRQ interrupt
5. Illegal opcode interrupt
6. Software interrupt (SWI)
The maskable interrupt sources have this priority arrangement:
1. IRQ
2. Real-time interrupt
3. Timer input capture 1
4. Timer input capture 2
5. Timer input capture 3
6. Timer output compare 1
7. Timer output compare 2
8. Timer output compare 3
9. Timer output compare 4
10. Timer input capture 4/output compare 5
11. Timer overflow
12. Pulse accumulator overflow
13. Pulse accumulator input edge
14. SPI transfer complete
15. SCI system (refer to Figure 5-7)
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
85