MC68711E20CFNE3 Datasheet, PDF (140/242 Pages) –

Timing Systems
9.4.10 Timer Interrupt Flag Register 2
Bits in this register indicate when certain timer system events have occurred. Coupled with the four
high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or
interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Address: $1025
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOF
Write:
RTIF PAOVF PAIF
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-20. Timer Interrupt Flag 2 Register (TFLG2)
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time (Periodic) Interrupt Flag
Refer to 9.5 Real-Time Interrupt (RTI).
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to 9.7 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to 9.7 Pulse Accumulator.
Bits [3:0] — Unimplemented
Always read 0
9.5 Real-Time Interrupt (RTI)
The real-time interrupt (RTI) feature, used to generate hardware interrupts at a fixed periodic rate, is
controlled and configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL)
register. The RTII bit in the TMSK2 register enables the interrupt capability. The four different rates
available are a product of the MCU oscillator frequency and the value of bits RTR[1:0]. Refer to Table 9-5,
which shows the periodic real-time interrupt rates.
Table 9-5. RTI Rates
RTR[1:0]
00
01
10
11
E = 3 MHz
2.731 ms
5.461 ms
10.923 ms
21.845 ms
E = 2 MHz
4.096 ms
8.192 ms
16.384 ms
32.768 ms
E = 1 MHz
8.192 ms
16.384 ms
32.768 ms
65.536 ms
E = X MHz
(E/2¹³)
(E/2¹⁴)
(E/2¹⁵)
(E/2¹⁶)
The clock source for the RTI function is a free-running clock that cannot be stopped or interrupted except
by reset. This clock causes the time between successive RTI timeouts to be a constant that is
M68HC11E Family Data Sheet, Rev. 5.1
140
Freescale Semiconductor