English
Language : 

MC68711E20CFNE3 Datasheet, PDF (37/242 Pages) –
Memory Map
Addr.
Register Name
Bit 7
6
5
4
3
2
1
$1025
Timer Interrupt Flag 2 Read: TOF
RTIF PAOVF
PAIF
(TFLG2) Write:
See page 142. Reset: 0
0
0
0
0
0
0
$1026
Pulse Accumulator Control Regis-
ter (PACTL)
See page 142.
Read:
Write:
Reset:
DDRA7
0
PAEN
0
PAMOD
0
PEDGE
0
DDRA3
0
I4/O5
0
RTR1
0
$1027
Pulse Accumulator Count Regis-
ter (PACNT)
See page 146.
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Indeterminate after reset
Bit 1
Serial Peripheral Control Register Read: SPIE
SPE
DWOM MSTR
$1028
(SPCR) Write:
See page 123. Reset: 0
0
0
0
CPOL
0
CPHA
1
SPR1
U
Serial Peripheral Status Register Read: SPIF
$1029
(SPSR) Write:
WCOL
MODF
See page 124. Reset: 0
0
0
0
0
0
0
Serial Peripheral Data I/O Regis- Read: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
$102A
ter (SPDR) Write:
See page 125. Reset:
Indeterminate after reset
$102B
Baud Rate Register
(BAUD)
See page 113.
Read:
Write:
Reset:
TCLR
0
SCP2(1)
0
SCP1
0
SCP0
0
RCKB
0
SCR2
U
SCR1
U
Serial Communications Control Read: R8
T8
$102C
Register 1 (SCCR1) Write:
M
WAKE
See page 110. Reset: I
I
0
0
0
0
0
Serial Communications Control Read: TIE
TCIE
RIE
ILIE
TE
RE
RWU
$102D
Register 2 (SCCR2) Write:
See page 111. Reset: 0
0
0
0
0
0
0
Serial Communications Status Read: TDRE
TC
$102E
Register (SCSR) Write:
See page 112. Reset: 1
1
RDRF
0
1. SCP2 adds ÷39 to SCI prescaler and is present only in MC68HC(7)11E20.
Serial Communications Data Reg-
$102F
ister (SCDR)
See page 110.
Read:
Write:
Reset:
R7/T7
R6/T6
R5/T5
IDLE
OR
0
0
R4/T4
R3/T3
Indeterminate after reset
NF
0
R2/T2
FE
0
R1/T1
Analog-to-Digital Control Status Read: CCF
$1030
Register (ADCTL) Write:
SCAN MULT
CD
CC
CB
See page 62. Reset: 0
0
Indeterminate after reset
= Unimplemented
I = Indeterminate after reset
R = Reserved U = Unaffected
Figure 2-7. Register and Control Bit Assignments (Sheet 4 of 6)
Bit 0
0
RTR0
0
Bit 0
SPR0
U
0
Bit 0
SCR0
U
0
SBK
0
0
R0/T0
CA
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
37