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MC68711E20CFNE3 Datasheet, PDF (46/242 Pages) – | |||
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Operating Modes and On-Chip Memory
Table 2-4. RAM Mapping
RAM[3:0]
Address
0000
$0000â$0xFF
0001
$1000â$1xFF
0010
$2000â$2xFF
0011
$3000â$3xFF
0100
$4000â$4xFF
0101
$5000â$5xFF
0110
$6000â$6xFF
0111
$7000â$7xFF
1000
$8000â$8xFF
1001
$9000â$9xFF
1010
$A000â$AxFF
1011
$B000â$BxFF
1100
$C000â$CxFF
1101
$D000â$DxFF
1110
$E000â$ExFF
1111
$F000â$FxFF
Table 2-5. Register Mapping
REG[3:0]
Address
0000
$0000â$003F
0001
$1000â$103F
0010
$2000â$203F
0011
$3000â$303F
0100
$4000â$403F
0101
$5000â$503F
0110
$6000â$603F
0111
$7000â$703F
1000
$8000â$803F
1001
$9000â$903F
1010
$A000â$A03F
1011
$B000â$B03F
1100
$C000â$C03F
1101
$D000â$D03F
1110
$E000â$E03F
1111
$F000â$F03F
2.3.3.3 System Configuration Options Register
The 8-bit, special-purpose system configuration options register (OPTION) sets internal system
configuration options during initialization. The time protected control bits, IRQE, DLY, and CR[1:0], can
be written only once after a reset and then they become read-only. This minimizes the possibility of any
accidental changes to the system configuration.
Address: $1039
Bit 7
6
5
4
3
Read:
ADPU
CSEL
IRQE(1)
DLY(1)
CME
Write:
2
1
Bit 0
CR1(1)
CR0(1)
Reset: 0
0
0
1
0
0
0
0
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during
special modes.
= Unimplemented
Figure 2-13. System Configuration Options Register (OPTION)
ADPU â Analog-to-Digital Converter Power-Up Bit
Refer to Chapter 3 Analog-to-Digital (A/D) Converter.
CSEL â Clock Select Bit
Selects alternate clock source for on-chip EEPROM charge pump. Refer to 2.5.1 EEPROM and
CONFIG Programming and Erasure for more information on EEPROM use.
CSEL also selects the clock source for the A/D converter, a function discussed in Chapter 3
Analog-to-Digital (A/D) Converter.
M68HC11E Family Data Sheet, Rev. 5.1
46
Freescale Semiconductor
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