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MC68711E20CFNE3 Datasheet, PDF (163/242 Pages) – | |||
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10.12 MC68L11E9/E20 Peripheral Port Timing
MC68L11E9/E20 Peripheral Port Timing
Characteristic(1) (2)
1.0 MHz
2.0 MHz
Symbol
Unit
Min Max Min Max
Frequency of operation
E-clock frequency
fo
dc
1.0
dc
2.0
MHz
E-clock period
Peripheral data setup time
MCU read of ports A, C, D, and E
tCYC
1000 â
500
â
ns
tPDSU
100
â
100
â
ns
Peripheral data hold time
MCU read of ports A, C, D, and E
tPDH
50
â
50
â
ns
Delay time, peripheral data write
tPWD = 1/4 tCYC+ 150 ns
MCU writes to port A
MCU writes to ports B, C, and D
tPWD
â
250
â
250
ns
â
400
â
275
Port C input data setup time
Port C input data hold time
Delay time, E fall to STRB
tDEB = 1/4 tCYC+ 150 ns
Setup time, STRA asserted to E fall(3)
tIS
60
â
60
â
ns
tIH
100
â
100
â
ns
tDEB
â
400
â
275
ns
tAES
0
â
0
â
ns
Delay time, STRA asserted to port C data output valid
Hold time, STRA negated to port C data
3-state hold time
tPCD
tPCH
tPCZ
â
100
â
100
ns
10
â
10
â
ns
â
150
â
150
ns
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, all timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted
2. Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers, respec-
tively.)
3. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one more cycle.
Figure 10-7. Port Read Timing Diagram
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
163
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