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MC68711E20CFNE3 Datasheet, PDF (172/242 Pages) – | |||
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Electrical Characteristics
10.18 MC68L11E9/E20 Serial Peirpheral Interface Characteristics
Num
Characteristic(1)
Frequency of operation
E clock
E-clock period
Operating frequency
Master
Slave
Cycle time
1
Master
Slave
2
Enable lead time(2)
Slave
3
Enable lag time(2)
Slave
Symbol
fo
tCYC
fop(m)
fop(s)
tCYC(m)
tCYC(s)
tlead(s)
tlag(s)
E9
Min
Max
dc
2.0
500
â
fo/32
fo/2
dc
fo
2
32
1
â
1
â
1
â
E20
Min
Max
dc
2.0
500
â
fo/128
fo/2
dc
fo
2
128
1
â
1
â
1
â
Unit
MHz
ns
MHz
tCYC
tCYC
tCYC
Clock (SCK) high time
4
Master
Slave
tw(SCKH)m
tw(SCKH)s
tCYCâ30
1/2
tCYCâ30
16 tCYC
â
tCYCâ30
1/2
tCYCâ30
64 tCYC
â
ns
Clock (SCK) low time
5
Master
Slave
tw(SCKL)m
tw(SCKL)s
tCYCâ30
1/2
tCYCâ30
16 tCYC
â
tCYCâ30
1/2
tCYCâ30
64 tCYC
â
ns
Data setup time (inputs)
6
Master
Slave
tsu(m)
40
â
40
â
ns
tsu(s)
40
â
40
â
Data hold time (inputs)
7
Master
Slave
th(m)
40
â
40
â
ns
th(s)
40
â
40
â
Slave access time
8
CPHA = 0
CPHA = 1
ta
0
50
0
50
ns
0
50
0
50
Disable time (hold time
9
to high-impedance state)
Slave
tdis
â
60
â
60
ns
10 Data valid(3) (after enable edge)
tv
â
60
â
60
ns
11
Data hold time (outputs)
(after enable edge)
tho
0
â
0
â
ns
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, all timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted
2. Time to data active from high-impedance state
3. Assumes 100 pF load on SCK, MOSI, and MISO pins
M68HC11E Family Data Sheet, Rev. 5.1
172
Freescale Semiconductor
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