MC68711E20CFNE3 Datasheet, PDF (173/242 Pages) –

MC68L11E9/E20 Serial Peirpheral Interface Characteristics
SS
INPUT
SCK
CPOL = 0
INPUT
SEE NOTE
SCK
CPOL = 1
OUTPUT
SEE NOTE
MISO
INPUT
MOSI
OUTPUT
SS IS HELD HIGH ON MASTER.
1
5
4
5
6
7
MSB IN
MASTER MSB OUT
4
BIT 6 . . . 1
11
BIT 6 . . . 1
LSB IN
10
MASTER LSB OUT
Note: This first clock edge is generated internally but is not seen at the SCK pin.
A) SPI Master Timing (CPHA = 0)
11 (REF)
SS
INPUT
SCK
CPOL = 0
INPUT
SCK
CPOL = 1
OUTPUT
MISO
INPUT
MOSI
OUTPUT
SS IS HELD HIGH ON MASTER.
1
5
4
5
4
MSB IN
10 (REF)
MASTER MSB OUT
6
BIT 6 . . . 1
11
BIT 6 . . . 1
SEE NOTE
SEE NOTE
LSB IN
10
7
11 (REF)
MASTER LSB OUT
Note: This first clock edge is generated internally but is not seen at the SCK pin.
B) SPI Master Timing (CPHA = 1)
Figure 10-15. SPI Timing Diagram (Sheet 1 of 2)
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
173