MC9S12DP512CPVE Datasheet, PDF (95/124 Pages) Freescale Semiconductor, Inc – MC9S12DP512 Device Guide V01.25

A.2 ATD Characteristics
MC9S12DP512 Device Guide V01.25
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V_SSA ≤ V_RL ≤ V_IN ≤ V_RH ≤ V_DDA. This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-8 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol Min
Typ
Max
Unit
Reference Potential
1D
Low
V_RL
V_SSA
-
V_DDA/2
V
High V_RH
V_DDA/2
V_DDA
V
2 C _{Differential Reference Voltage}¹
V_RH-V_RL
4.50
5.00
5.25
V
3 D ATD Clock Frequency
f_ATDCLK
0.5
-
2.0
MHz
ATD 10-Bit Conversion Period
4D
Clock Cycles^{2 N}CONV10
14
-
28
Cycles
Conv, Time at 2.0MHz ATD Clock f_ATDCLK T_CONV10
7
14
µs
ATD 8-Bit Conversion Period
5D
Clock Cycles^{(2) N}CONV8
12
-
26
Cycles
Conv, Time at 2.0MHz ATD Clock f_ATDCLK T_CONV8
6
13
µs
6 D Recovery Time (V_DDA=5.0 Volts)
t_REC
-
-
20
µs
7 P Reference Supply current 2 ATD blocks on
I_REF
-
-
0.750
mA
8 P Reference Supply current 1 ATD block on
I_REF
-
-
0.375
mA
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
A.2.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R_S
95