MC9S12DP512CPVE Datasheet, PDF (120/124 Pages) Freescale Semiconductor, Inc – MC9S12DP512 Device Guide V01.25

MC9S12DP512 Device Guide V01.25
Table A-21 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, C_LOAD = 50pF
Num C
Rating
Symbol Min
Typ
Max
32 D NOACC hold time
t_NOH
2
-
-
33 D IPIPE[1:0] delay time
t_P0D
2
-
7
34 D IPIPE[1:0] valid time to E rise (PW_EL–t_P0D)
t_P0V
11
-
-
35 D IPIPE[1:0] delay time⁽¹⁾ (PW_EH-t_P1V)
t_P1D
2
-
7
36 D IPIPE[1:0] valid time to E fall
t_P1V
11
-
-
NOTES:
1. Affected by clock stretch: add N x t_cyc where N=0,1,2 or 3, depending on the number of clock stretches.
Unit
ns
ns
ns
ns
ns